Semidynamics

WATCH CPS 22

Memory-centric AI inference chips for large-scale applications. Products include Atrevido, Coherent Tensor Unit, and 3nm AI inference silicon

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Researched 2026-04-08 ● Current
Semidynamics — robotics.press intelligence card

Semidynamics pursues a technically credible architectural thesis—coherent RISC-V CPU+vector+NPU IP for edge AI inference—aligned with structural demand in autonomous systems and European sovereignty agendas. However, with only ~13 employees, no publicly verified paying customers or production deployments, opaque financials, and intense competition from better-capitalized RISC-V peers and incumbents, the company remains a high-beta, early-stage bet whose investability hinges entirely on near-term proof of commercial traction and software stack maturity.

Moat NARROW

- Claimed first fully-coherent RISC-V Tensor Unit (Oct 2023) could be a differentiator if validated and patented - Wide vector unit capability (up to 2048-bit SIMD) tailored for AI/HPC throughput on RISC-V - Native Arm CHI interface for coherency and system integration, reducing adoption friction for SoC designers - Ecosystem partnerships (Arteris, sureCore, Baya) create some integration lock-in for early adopters

Management ADEQUATE

Founder/CEO Roger Espasa leads a technically ambitious team, but limited public biographical detail and no disclosed prior tapeout track record or major IP adoption history make leadership credibility a key diligence gap. The 13-person team implies hands-on leadership across architecture and partnerships, which accelerates decisions but risks bandwidth constraints across sales, software enablement, and customer support.

Financials OPAQUE
Bull Case

Coherent CPU+vector+AI acceleration architecture (Cervell NPU, coherent tensor unit) is well-suited to low-latency, power-efficient edge inference demanded by robotics and autonomous systems (HTEC 2026 edge AI thesis)

Ecosystem partnerships with Arteris IP (NoC/system integration), sureCore (multi-port memory), and Baya Systems reduce SoC integration friction and signal credibility to potential licensees

Strong alignment with EU technology sovereignty and defense compute agendas, potentially unlocking non-dilutive grants, procurement pathways, and defense-adjacent demand (Defence Finance Monitor 2026)

February 2026 announcement of 3nm AI inference silicon and full-stack systems at TSMC suggests ambition to demonstrate advanced-node PPA, a meaningful proof point if validated

RISC-V macro tailwinds: open ISA adoption accelerating across edge and AI workloads, with industry moving away from proprietary architectures, expanding Semidynamics' addressable market

IP licensing model is structurally less capital-intensive than fabless chip production, enabling lean operations if the company remains focused on IP rather than productized silicon

Bear Case

No publicly verified paying IP licensees, production deployments, or named customers in any vertical—commercial traction is entirely unsubstantiated as of April 2026

Headcount of only 13 employees (July 2024) severely constrains capacity for parallel customer engagements, software toolchain development, and compiler/runtime investment—the critical bottleneck for edge AI adoption (HTEC 2026)

Financial opacity: funding amounts undisclosed or inconsistently reported, no revenue data, and unclear runway—especially concerning if the company is pursuing 3nm tapeouts with significant NRE costs (Deloitte 2026 supply chain constraints)

Competitive intensity from established RISC-V IP vendors (SiFive, Andes, Ventana) and large incumbents (Arm, Qualcomm, NVIDIA) who outspend on software ecosystems, compilers, and developer tools

3nm silicon claims require validation of foundry commitments, PPA benchmarks, and cost basis; a 13-person company attempting leading-edge tapeouts faces severe supply-chain and financial risk (Deloitte 2026 zero-sum capacity)

Software stack maturity is undemonstrated publicly—no SDK releases, no reference designs, no independent benchmarks on representative robotics/autonomous workloads

Key Risks

No verifiable commercial revenue or paying IP licensees—business model remains unproven

3nm silicon ambitions could dramatically increase cash burn without clear foundry commitments or customer pre-orders to de-risk NRE

Software ecosystem immaturity: edge AI adoption is gated by toolchains, compilers, and framework integration, not just hardware PPA (HTEC 2026)

Severe competitive pressure from better-funded RISC-V IP firms and incumbent architectures with mature developer ecosystems

Funding runway is opaque; grant-based financing may not scale to support advanced-node tapeouts and team expansion

Key-person risk with a 13-employee company dependent on founder/CEO technical vision

Catalysts

Announcement of a named, paying IP licensee or auditable design-win count in robotics, automotive, or industrial automation verticals

Independent PPA benchmarks on 3nm silicon for representative edge inference workloads (perception, sensor fusion, recommendation)

EU grant awards or defense procurement framework inclusion validating sovereignty alignment

SDK or developer toolkit release with ONNX runtime integration or optimized libraries for common autonomous systems workloads

Meaningful headcount expansion, particularly in compiler/runtime engineering and customer-facing roles, signaling commercial traction

Irreplaceability 3
Market Weight
Tech Differentiation
Operational Deployment
Strategic Momentum
Ecosystem Influence
Coverage Necessity
Fin. Valuation
Fin. Revenue
TypeQuick Research
Published2026-04-08
Length2,294 words · 10 min read
Sources13 sources cited
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Generated by automated research. Cross-reference with primary sources before investment decisions.

Atrevido Software · PROTOTYPE
└─ High-performance out-of-order RISC-V CPU cores designed for AI and HPC workloads with native CHI interface support for coherency and system integration. Referenced in secondary analysis as the Atrevido series; described as high-bandwidth, configurable RISC-V processor IP. Third-party commentary suggests up to 2048-bit SIMD vector configurations aimed at parallelizable AI and signal-processing workloads. Positioned within European Strategic Autonomy and AI compute sovereignty narratives.
Cervell Software · PROTOTYPE · Launched 2025
└─ All-in-one RISC-V NPU integrating CPU cores, vector units, and AI acceleration in a coherent subsystem for edge inference workloads. Unveiled via headline in May 2025. Described as an all-in-one RISC-V NPU combining CPU cores, vector units, and AI acceleration in a coherent subsystem. A 2026 press round-up references 'full-stack systems' suggesting a software toolchain/runtime push, though this is not yet substantiated by accessible public documentation. Software stack details remain limited publicly.
Coherent Tensor Unit Software · PROTOTYPE · Launched 2023
└─ Fully-coherent RISC-V tensor unit designed as a building block for AI inference acceleration within the Cervell NPU platform. Announced October 2023 with the claim of being the 'first fully-coherent RISC-V Tensor Unit.' Positions coherent AI acceleration as a key differentiator for Semidynamics. Technical details are noted as unverified publicly in the report and warrant confirmation via primary company documentation.
3nm AI Inference Silicon Software · CONCEPT · Launched 2026
└─ Advanced-node silicon implementation of Semidynamics' RISC-V CPU and AI acceleration architecture at 3nm process technology, claimed to include full-stack systems support. Announced via PR headlines in February 2026 with TSMC referenced as foundry partner. Represents a potential step-change from pure IP licensing toward advanced-node silicon productization. The report flags that the maturity level (internal validation vs. commercial productization), PPA metrics, foundry commitments, NRE costs, and customer intent all require validation. Primary press releases and technical documentation were not available in the report's dataset and should be sought directly for confirmation.
Roger Espasa Founder and CEO